1. Field of the Invention
The present invention relates to a high-speed address translation system. Particularly, it relates to memory allocation in a translation lookaside buffer (below, TLB) provided in a memory management unit (below, MMU) in a computer system. The high-speed address translation system according to the present invention can be advantageously utilized in the field of an electronic switching system formed of an online real-time system having high reliability.
2. Description of the Related Art
In general, a TLB is provided in order to dynamically access between a virtual address space (or, a logical address space) and a physical address space. In this case, a predetermined program is executed with reference to the virtual address space, and an actual content of the program is arranged in the physical address space. The TLB is formed by a plurality of entries and usually provided within a MMU, as hardware, in a normal computer system.
For example, in general, a system utilizing an address translation system is formed by a logical address space, a MMU connected to the logical address space and a physical address space connected to the MMU for executing an actual program (see FIG. 11).
In this structure, the address space is managed based on a minimum unit of the memory management which is called a "page". Further, the TLB stores corresponding relationships between the virtual address and the physical address in accordance with the page, and translates the virtual address to the physical address in response to an instruction access or a data access.
Since the TLB is formed by the hardware as mentioned above, it has a finite space which can be utilized as a resource. Accordingly, contents of the TLB must be updated in accordance with frequency in use thereof. For example, when an address to be translated from the virtual address to the physical address is missed (i.e., not hit) in the TLB, that address information is provided from a main memory to the TLB.
On the other hand, in the normal computer system, a predetermined program is loaded on the memory in accordance with a request from an operator, and the memory is released after execution of the predetermined program. Accordingly, in a conventional art, the page size is fixed to one kind of size as the minimum unit to be managed in order to raise efficiency in use of the memory.
However, in an online real-time system, such as a switching system, a program, in which a time-critical process is required, is loaded on an address space which was previously allocated. Further, in the time-critical process, when the address is missed in the TLB (below, TLB miss-hit), the TLB miss-hit is processed dynamically either by using a predetermined hardware, or by using an operating system (OS) as a trap operation (i.e., an interrupt to the OS when the TLB miss-hit occurs). In this case, however, since the above process for the TLB miss-hit is not recognized by an application program (i.e., the TLB miss-hit is "invisible" to an operator), an unexpected fall in performance occurs in the system.
The present invention aims to solve the above mentioned problems in the conventional art. That is, in an online real-time system required for high reliability, such as a switching system, the present invention aims to provide a high-speed address translation system in which it is possible to eliminate an overhead due to the TLB miss-hit in very important process, such as a basic call process in the exchange (in other word, the TLB miss-hit can be recognized by the operator) when executing the address translation in the present invention. According to the present invention, it is possible to considerably improve performance of the system, and to raise precision of expected performance without consideration of the TLB miss-hit in the real-time process.